X
About the project
WP1 Project Management T1.1 Overall project coordination T1.2 Operational project management T1.3 Quality & innovation management, risk assessment T1.4 Research Data Management
WP2 Requirements T2.1 Definition of the requirements of the photonics technologies T2.2 Definition of the requirements of the photonics circuits T2.3 Definition of the requirements of the photonics applications T2.4 Sustainability improvement of the silicon photonics value chain
WP3 Photonics Technologies T3.1 SiPho Technology Development T3.2 Photonics substrates technology development T3.3 Integration of non-silicon materials at wafer level
WP4 Photonics Circuits T4.1 PIC100 circuits design T4.2 Path Finding to PIC200 circuits design T4.3 Photonics Tools T4.4 Photonics Packaging & Assembly T4.5 EIC Circuits Development
WP5 Photonics Applications T5.1 Demonstrators for Datacom & Hyperscaler T5.2 Demonstrators for AI Accelerator T5.3 Demonstrators for sensing T5.4 Telecom Demonstrator
WP6 Exploitation & Dissemination T6.1 External communication and dissemination of the results T6.2 Exploitation of STARLight results and business plans. T6.3 Education and Training
T4.5 EIC Circuits Development

Photonic ICs designed for high RF-performance in PIC100 and especially PIC200 technology must be accompanied by highly optimized and customized electrical ICs that harness this performance and provide the connection to the host system, such as a switch or a server. Close proximity between PIC and EIC is a prerequisite for high bandwidth and signal integrity and relies on compact packaging methods.

Active photonic devices like modulators and PDs, especially with bandwidth >100 GHz for 200 GBd applications demand for very close integration with the RF-amplifier circuits to achieve high signal integrity, low parasitics and reduced interconnect inductance. Therefore, the activities in task 4.5 focus on driver and TIA circuit development in different technologies and for different use cases. While subtask T4.5.1 realizes designs using InP HBT technology for high-speed and high swing circuits, subtask T4.5.3 is targeting driver and TIA designs in SiGe-BiCMOS technology for die-stacking with the PIC. A low-power solution for co-packaging applications using resonant modulator types is developed in T4.5.2. Electrical models from the driver and TIA designs are provided as deliverables for the system-level simulations in T4.2.1. In T4.5.4 a driver and TIA in SiGe-BiCMOS are developed in collaboration with T4.1.4 for the analog optical interconnect demonstrator in T5.4.3.

Leader : STM
Involved Partners : III-V LAB, STM, SICOYA, CEA, ERICSSON-SE