Even though PIC200 technology is not expected to reach a TRL level above 5 within STARLight timeframe, it is nonetheless very important to provide tangible output of PIC200 on component level as soon as possible through several key silicon photonics building blocks. The ultimate objective is to minimize the time gap between PIC100 and PIC200 generations and thus maintain Europe leadership brought by PIC100 technology.

Based on the expected PIC200 maturity level resulting from the process and integration related activities in WP3 and WP4 T4.2.2-8, the outcome of this task does not target application-ready device circuits, but the evaluation of multiple laser (T4.2.3-7) and 200 GBd-capable modulator (T4.2.2/5/6/8) integration approaches. This will be achieved by designing and testing DOEs on building-block level and including detailed building-block models in circuit and system-level simulations in subtask 4.2.1. While different application specific laser and modulator requirements need to be considered, the scalability of the integration processes is a key factor.